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d여기에서 verilog code for RAM – ram verilog code 주제에 대한 세부정보를 참조하세요
Random access memory
ram verilog code 주제에 대한 자세한 내용은 여기를 참조하세요.
Verilog Single Port RAM – ChipVerify
Design module single_port_sync_ram # (parameter ADDR_WIDTH = 4, parameter DATA_WIDTH = 32, parameter DEPTH = 16 ) ( input clk, input [ADDR_WIDTH-1:0] addr, …
Source: www.chipverify.com
Date Published: 6/27/2021
View: 2878
Hướng dẫn – Thiết kế bộ RAM dùng verilog | Vi mạch
(COPY SÁCH ^_^ ) . Single Port RAM Synchronous Read/Write. Mã: module ram_sp_sr_sw ( clk , // Clock Input address , // Address Input data , …
Source: vimach.net
Date Published: 7/19/2021
View: 7052
Synchronous Static RAM – Verilog for Beginners
Verilog Module ; Synchronous SRAM. This ; Synchronous SRAM can store ; eight 8-bit values. The ; Synchronous SRAM module consists of a ; 8-bit data input line, …
Source: esrd2014.blogspot.com
Date Published: 2/6/2021
View: 5306
Verilog code for RAM – Tutorials and programs
verilog tutorial and programs with testbench code – Random Acess Memory.
Source: techmasterplus.com
Date Published: 1/7/2022
View: 7442
Verilog HDL: Single-Port RAM Design Example – Intel
Synthesis tools are able to detect single-port RAM designs in the HDL code and automatically infer either the altsyncram or the altdpram megafunctions, …
Source: www.intel.com
Date Published: 4/24/2022
View: 4174
Verilog memory code. Synchronous Random Access Memory …
Verilog RAM RTL code. Implement synchronous RAM (Random Access Memory) and also prove a test-bench to valate it. module mem_ram_sync( clk, rst, read_rq, …
Source: www.fullchipdesign.com
Date Published: 6/27/2022
View: 4565
RAMs
Following is the Verilog code for a dual-port RAM with synchronous read (read through). … Note The two RAM ports may be synchronized on distinct clocks, as …
Source: www.csit-sun.pub.ro
Date Published: 5/16/2021
View: 9646
verilog code of RAM – Xilinx Support
i write the verilog code of RAm having both write enable and read enable…..in simulation i am getting correct result…but in test bench first i have to …
Source: support.xilinx.com
Date Published: 10/27/2021
View: 9332
Single Port RAM Synchronous Read/Write – ASIC World
This page contains Verilog tutorial, Verilog Syntax, Verilog Quick Reference, PLI, modeling memory and FSM, Writing Testbenches in Verilog, Lot of Verilog …
Source: www.asic-world.com
Date Published: 6/5/2022
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주제와 관련된 이미지 ram verilog code
주제와 관련된 더 많은 사진을 참조하십시오 verilog code for RAM. 댓글에서 더 많은 관련 이미지를 보거나 필요한 경우 더 많은 관련 기사를 볼 수 있습니다.
주제에 대한 기사 평가 ram verilog code
- Author: gnaneshwar chary
- Views: 조회수 9,127회
- Likes: 좋아요 120개
- Date Published: 2020. 4. 11.
- Video Url link: https://www.youtube.com/watch?v=G9IPd9Bm_7Q
What is single port RAM?
The Single Port RAM block models RAM that supports sequential read and write operations. If you want to model RAM that supports simultaneous read and write operations, use the Dual Port RAM block or Simple Dual Port RAM block.
How do I create a memory in Verilog?
To help modeling of memory, Verilog provides support for two dimensions arrays. Behavioral models of memories are modeled by declaring an array of register variables; any word in the array may be accessed using an index into the array. A temporary variable is required to access a discrete bit within the array.
What is single port RAM and dual port?
single port RAM can be accessed at one address at one time, thus you can read/write only one memory cell during each clock cycle. Dual port RAM has ability to simultaneously read and write different memory cells at different addresses.
What is true Dual Port RAM?
Defines a memory, of various implementation, with two read/write ports (2WR), separately addressed, with a common clock. Common data width on both ports. There is no synchronous clear on the output: In Quartus at least, any register driving it cannot be retimed, and it may not be as portable.
What is SRAM and DRAM in computer?
SRAM (static RAM) is a type of random access memory (RAM) that retains data bits in its memory as long as power is being supplied. Unlike dynamic RAM (DRAM), which must be continuously refreshed, SRAM does not have this requirement, resulting in better performance and lower power usage.
What is a DRAM computer?
Dynamic random access memory (DRAM) is a type of semiconductor memory that is typically used for the data or program code needed by a computer processor to function. DRAM is a common type of random access memory (RAM) that is used in personal computers (PCs), workstations and servers.
What is memory in Verilog?
A register in a memory (that is, RAM or ROM) block which contains the same range of bits as the other registers in the memory. For example, the memory reg [5:0] EXAMPLE [0:2] defines 3 memory words, each containing a bit range of 5 to 0 .
Is $Readmemh synthesizable?
$readmemh is not synthesizeable. It is used for simulation or behavioural code only.
What is in Verilog syntax?
Lexical conventions in Verilog are similar to C in the sense that it contains a stream of tokens. A lexical token may consist of one or more characters and tokens can be comments, keywords, numbers, strings or white space. All lines should be terminated by a semi-colon ; .
What are types of RAM?
- DRAM (pronounced DEE-RAM), is widely used as a computer’s main memory. …
- SRAM (pronounced ES-RAM) is made up of four to six transistors.
What is dual read RAM?
Dual-ported RAM (DPRAM) is a type of random-access memory that allows multiple reads or writes to occur at the same time, or nearly the same time, unlike single-ported RAM which allows only one access at a time.
What is pseudo dual port SRAM?
A pseudo-dual-port (PDP) memory such as a PDP SRAM is provided that independently controls the bit line precharging and the sense amplifier precharging to increase memory operating speed while eliminating or reducing the discharge of crowbar current.
What is difference between dual port and two port memory?
two-port has one read port and one write port. dual-port has two ports that can be configured as read+read, write+write, read+write.
What is the difference between single port and dual port VW engine?
Dual port heads flow a bit better for more higher rpm power. Single port heads are good for a little more torque, and have a bit less high end power.
What is pseudo dual port SRAM?
A pseudo-dual-port (PDP) memory such as a PDP SRAM is provided that independently controls the bit line precharging and the sense amplifier precharging to increase memory operating speed while eliminating or reducing the discharge of crowbar current.
Verilog Single Port RAM
Verilog Single Port RAM
Design
module single_port_sync_ram # (parameter ADDR_WIDTH = 4, parameter DATA_WIDTH = 32, parameter DEPTH = 16 ) ( input clk, input [ADDR_WIDTH-1:0] addr, inout [DATA_WIDTH-1:0] data, input cs, input we, input oe ); reg [DATA_WIDTH-1:0] tmp_data; reg [DATA_WIDTH-1:0] mem [DEPTH]; always @ (posedge clk) begin if (cs & we) mem[addr] <= data; end always @ (posedge clk) begin if (cs & !we) tmp_data <= mem[addr]; end assign data = cs & oe & !wr ? tmp_data : 'hz; endmodule Testbench
Hướng dẫn – Thiết kế bộ RAM dùng verilog
1.Khái niệm
2, Phân loại.
Mã: module ram_sp_sr_sw ( clk , // Clock Input address , // Address Input data , // Data bi-directional cs , // tín hiệu điều khiển cho phép đọc và ghi we , // Write Enable/Read Enable oe // Output Enable ); parameter DATA_WIDTH = 8 ; parameter ADDR_WIDTH = 8 ; parameter RAM_DEPTH = 1 << ADDR_WIDTH; //--------------Input Ports----------------------- input clk ; input [ADDR_WIDTH-1:0] address ; input cs ; input we ; input oe ; //--------------Inout Ports----------------------- inout [DATA_WIDTH-1:0] data ; //--------------Internal variables---------------- reg [DATA_WIDTH-1:0] data_out ; reg [DATA_WIDTH-1:0] mem [0:RAM_DEPTH-1]; //--------------Code Starts Here------------------ // Tri-State Buffer control // output : When we = 0, oe = 1, cs = 1 assign data = (cs && oe && ! we) ? data_out : 8'bz; // Memory Write Block // Write Operation : When we = 1, cs = 1 always @ (posedge clk) begin : MEM_WRITE if ( cs && we ) begin mem[address] = data; end end // Memory Read Block // Read Operation : When we = 0, oe = 1, cs = 1 always @ (posedge clk) begin : MEM_READ if (cs && ! we && oe) begin data_out = mem[address]; end else ; end endmodule Mã: module ram_dp_sr_sw ( clk , // Clock Input address_0 , // address_0 Input data_0 , // data_0 bi-directional cs_0 , // Chip Select we_0 , // Write Enable/Read Enable oe_0 , // Output Enable address_1 , // address_1 Input data_1 , // data_1 bi-directional cs_1 , // Chip Select we_1 , // Write Enable/Read Enable oe_1 // Output Enable ); parameter data_0_WIDTH = 8 ; parameter ADDR_WIDTH = 8 ; parameter RAM_DEPTH = 1 << ADDR_WIDTH; //--------------Input Ports----------------------- input [ADDR_WIDTH-1:0] address_0 ; input cs_0 ; input we_0 ; input oe_0 ; input [ADDR_WIDTH-1:0] address_1 ; input cs_1 ; input we_1 ; input oe_1 ; //--------------Inout Ports----------------------- inout [data_0_WIDTH-1:0] data_0 ; inout [data_0_WIDTH-1:0] data_1 ; //--------------Internal variables---------------- reg [data_0_WIDTH-1:0] data_0_out ; reg [data_0_WIDTH-1:0] data_1_out ; reg [data_0_WIDTH-1:0] mem [0:RAM_DEPTH-1]; //--------------Code Starts Here------------------ // Memory Write Block // Write Operation : When we_0 = 1, cs_0 = 1 always @ (posedge clk) begin : MEM_WRITE if ( cs_0 && we_0 ) begin mem[address_0] <= data_0; end else if (cs_1 && we_1) begin mem[address_1] <= data_1; end end // Tri-State Buffer control // output : When we_0 = 0, oe_0 = 1, cs_0 = 1 assign data_0 = (cs_0 && oe_0 && ! we_0) ? data_0_out : 8'bz; // Memory Read Block // Read Operation : When we_0 = 0, oe_0 = 1, cs_0 = 1 always @ (posedge clk) begin : MEM_READ_0 if (cs_0 && ! we_0 && oe_0) begin data_0_out <= mem[address_0]; end else begin data_0_out <= 0; end end //Second Port of RAM // Tri-State Buffer control // output : When we_0 = 0, oe_0 = 1, cs_0 = 1 assign data_1 = (cs_1 && oe_1 && ! we_1) ? data_1_out : 8'bz; // Memory Read Block 1 // Read Operation : When we_1 = 0, oe_1 = 1, cs_1 = 1 always @ (posedge clk) begin : MEM_READ_1 if (cs_1 && ! we_1 && oe_1) begin data_1_out <= mem[address_1]; end else begin data_1_out <= 0; end end endmodule 3,Một số ví dụ khác. Mã: module ram_single(q, a, d, we, clk); output[7:0] q; input [7:0] d; input [6:0] a; input we, clk; reg [7:0] mem [127:0]; always @(posedge clk) begin if (we) mem[a] <= d; q <= mem[a]; end endmodule Mã: module bram_tdp #( parameter DATA = 72, parameter ADDR = 10 ) ( // Port A input wire a_clk, input wire a_wr, input wire [ADDR-1:0] a_addr, input wire [DATA-1:0] a_din, output reg [DATA-1:0] a_dout, // Port B input wire b_clk, input wire b_wr, input wire [ADDR-1:0] b_addr, input wire [DATA-1:0] b_din, output reg [DATA-1:0] b_dout ); // Shared memory reg [DATA-1:0] mem [(2**ADDR)-1:0]; // Port A always @(posedge a_clk) begin a_dout <= mem[a_addr]; if(a_wr) begin a_dout <= a_din; mem[a_addr] <= a_din; end end // Port B always @(posedge b_clk) begin b_dout <= mem[b_addr]; if(b_wr) begin b_dout <= b_din; mem[b_addr] <= b_din; end end endmodule =D=D=D ¤RAM viết tắt của cụm từ Random Access Memory, bộ nhớ truy cập ngẫu nhiên. ¤Thời gian đọc và ghi với các ô nhớ là như nhau, dù đang ở bất kỳ vị trí nào trên bộ nhớ, mỗi ô nhớ của RAM đều có một địa chỉ. ¤Thông thường mỗi ô nhớ là một Byte. ¤RAM có cơ chế đọc ghi dữ liệu hoàn toàn khác với băng, đĩa có cơ chế đọc ghi tuần tự. ¤RAM khác với ROM là bộ nhớ chỉ đọc.- Single port RAM là RAM chỉ có một kênh đọc và ghi, một đường vào địa chỉ, cácđộng tác đọc ghi trên kênh này chỉ có thể thực hiện lần lượt.- Dual-port RAM là RAM có hai kênh đọc ghi riêng biệt tương ứng hai kênh địa chỉ, các kênh đọc ghi này có thể dùng chung xung nhịp đồng bộ cũng có thể không dung chung. Đối với Dual-port RAM có thể đọc và ghi đồng thời trên hai kênh.- Synchronous RAM - RAM đồng bộ là RAM thực hiện thao tác đọc hoặc ghi đồng bộ.- Asynchronous RAM- RAM không đồng bộ là RAM thực hiện thao tác đọc hoặc ghikhông đồng bộ, thời gian kể từ khi có các tín hiệu yêu cầu đọc ghi cho tới khi thao tác thực hiện xong thuần túy là trễ tổ hợp.-- Khối RAM có 2 thành phần chính là khối giải mã địa chỉ và dãy các thanh ghi, khối giải mã địa chỉ sẽ đọc địa chỉ và quyết định sẽ truy cập tới vị trí thanh ghi nào để thực hiện thao tác đọc hoặc ghi. Kích thước của khối RAM thường được ký hiệu là Mx N-bit trong đó M là số lượng thanh ghi, N là số bit trên 1 thanh ghi. Ví dụ 128 x 8 bit là khối RAM gồm 128 thanh ghi, mỗi thanh ghi 8 bit. Số bit cần thiết cho kênh địa chỉ là ADDR_WIDTH = [log2 M], nếu M = 128 nên số ADDR_WIDTH = 7. (COPY SÁCH ^_^ ) .-- Các tín hiệu điều khiển thao tác đối với RAM bao gồm CS – chip select, với mọithao tác thì đều yêu cầu CS phải ở mức cao. WE – write enable bằng 1 nếu cần ghi dữ liệu vào RAM. Tín hiệu OE – output enable bằng 1 nếu là đọc dữ liệu từ RAM, với thiết kế như vậy thì WE và OE không bao giờ đồng thời bằng 1.
Single port RAM
The HDL block property, RAMArchitecture , enables or suppresses generation of clock enable logic for all RAM blocks in a subsystem. You can set RAMArchitecture to the following values:
WithClockEnable (default): Generates RAM using HDL templates that include a clock enable signal, and an empty RAM wrapper.
WithoutClockEnable : Generates RAM without clock enables, and a RAM wrapper that implements the clock enable logic.
Some synthesis tools do not infer RAM with a clock enable. If your synthesis tool does not support RAM structures with a clock enable, and cannot map your generated HDL code to FPGA RAM resources, set RAMArchitecture to WithoutClockEnable .
To learn how to generate RAM without clock enables for your design, see the Getting Started with RAM and ROM example. To open the example, at the command prompt, enter:
Modeling Memories And FSM Part
Memory Modeling To help modeling of memory, Verilog provides support for two dimensions arrays. Behavioral models of memories are modeled by declaring an array of register variables; any word in the array may be accessed using an index into the array. A temporary variable is required to access a discrete bit within the array. Syntax reg [wordsize:0] array_name [0:arraysize] Examples Declaration reg [7:0] my_memory [0:255]; Here [7:0] is the memory width and [0:255] is the memory depth with the following parameters: Width : 8 bits, little endian
Depth : 256, address 0 corresponds to location 0 in the array. Storing Values my_memory[address] = data_in; Reading Values data_out = my_memory[address]; Bit Read Sometimes there may be need to read just one bit. Unfortunately Verilog does not allow to read or write only one bit: the workaround for such a problem is as shown below. data_out = my_memory[address]; data_out_it_0 = data_out[0]; Initializing Memories A memory array may be initialized by reading memory pattern file from disk and storing it on the memory array. To do this, we use system tasks $readmemb and $readmemh. $readmemb is used for binary representation of memory content and $readmemh for hex representation. Syntax $readmemh(“file_name”,mem_array,start_addr,stop_addr); Note : start_addr and stop_addr are optional. Example – Simple memory 1 module memory(); 2 reg [7:0] my_memory [0:255]; 3 4 initial begin 5 $readmemh ( “memory.list” , my_memory); 6 end 7 endmodule You could download file memory.v here Example – Memory.list file 1 //Comments are allowed 2 1100_1100 // This is first address i.e 8’h00 3 1010_1010 // This is second address i.e 8’h01 4 @ 55 // Jump to new address 8’h55 5 0101_1010 // This is address 8’h55 6 0110_1001 // This is address 8’h56 You could download file memory.list here $readmemh system task can also be used for reading testbench vectors. I will cover this in detail in the test bench section … when I find time. Refer to the examples section for more details on different types of memories.
RAM True Dual Port
Source
License
Index
True Dual-Ported RAM
Defines a memory, of various implementation, with two read/write ports (2WR), separately addressed, with a common clock. Common data width on both ports. There is no synchronous clear on the output: In Quartus at least, any register driving it cannot be retimed, and it may not be as portable. Instead, use separate logic (e.g.: an Annuller) to zero-out the output down the line.
Write Forwarding
The READ_NEW_DATA parameter control the behaviour of simultaneous reads and writes to the same address. This is the most important parameter when considering what kind of memory block the CAD tool will infer.
READ_NEW_DATA = 0 describes a memory which returns the OLD value (in the memory) on coincident read and write (no write-forwarding). This is well-suited for LUT-based memory, such as MLABs.
describes a memory which returns the OLD value (in the memory) on coincident read and write (no write-forwarding). This is well-suited for LUT-based memory, such as MLABs. READ_NEW_DATA = 1 (or any non-zero value) describes a memory which returns NEW data (from the write) on coincident read and write, usually by inferring some surrounding write-forwarding logic. Good for dedicated Block RAMs, such as M10K.
The inferred write-forwarding logic also allows the RAM to operate at higher frequency, since a read corrupted by a simultaneous write to the same address will be discarded and replaced by the write value at the output mux of the forwarding logic. Otherwise, the RAM must internally perform the write on one edge of the clock, and the read on the other, which requires a longer cycle time.
Quartus
For Quartus, if you do not want write-forwarding, but still get the higher speed at the price of indeterminate behaviour on coincident read/writes, use “no_rw_check” as part of the RAMSTYLE (e.g.: “M10K, no_rw_check”). Depending on the FPGA hardware, this may also help when returning OLD data. If that fails, add this setting to your Quartus project: set_global_assignment -name ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS OFF to disable creation of write-forwarding logic, as Quartus ignores the “no_rw_check” RAMSTYLE for M10K BRAMs.
Vivado
Vivado uses a different mechanism to control write-forwarding: set RW_ADDR_COLLISION to “yes” to force the inference of write forwarding logic, or “no” to prevent it. Otherwise, set it to “auto”.
`default_nettype none module RAM_True_Dual_Port #( parameter WORD_WIDTH = 0, parameter ADDR_WIDTH = 0, parameter DEPTH = 0, parameter RAMSTYLE = “”, parameter READ_NEW_DATA = 0, parameter RW_ADDR_COLLISION = “”, parameter USE_INIT_FILE = 0, parameter INIT_FILE = “”, parameter [WORD_WIDTH-1:0] INIT_VALUE = 0 ) ( input wire clock, input wire wren_A, input wire [ADDR_WIDTH-1:0] addr_A, input wire [WORD_WIDTH-1:0] write_data_A, output reg [WORD_WIDTH-1:0] read_data_A, input wire wren_B, input wire [ADDR_WIDTH-1:0] addr_B, input wire [WORD_WIDTH-1:0] write_data_B, output reg [WORD_WIDTH-1:0] read_data_B ); localparam ZERO = {WORD_WIDTH{1’b0}}; initial begin read_data_A = ZERO; read_data_B = ZERO; end
Set the ram style to control implementation. See your CAD tool documentation for available options.
(* ramstyle = RAMSTYLE *) // Quartus (* ram_style = RAMSTYLE *) // Vivado (* rw_addr_collision = RW_ADDR_COLLISION *) // Vivado
This is the RAM array proper. Not how we access or implement it.
reg [WORD_WIDTH-1:0] ram [DEPTH-1:0];
The only difference selected by READ_NEW_DATA is the use of blocking/non-blocking assignments. Blocking assignments make the write happen logically before the read, as ordered here, and thus describe write-forwarding behaviour where the read takes data from the write port. Non-blocking assignments make read and write take effect simultaneously at the end of the always block, so the read takes its data from the memory.
UPDATE: Since I originally wrote this code, over 10 years ago, I have learnt that using blocking assignments inside a clocked always block may cause simulation race conditions, depending on the order of evaluation of the always blocks (see IEEE Standard 1364-2001, Section 5, “Scheduling Semantics”). However, I have never seen such race conditions happen, possibly because of how this and other code was written (e.g.: it’s in its own module, which affects event scheduling). I also could not find a simpler and cleaner way to express “write-before-read” behaviour while leaving the CAD tool free to infer RAM as it could. Finally, FPGA Block RAMs, and their CAD tools, have since changed and may no longer infer memory in the same way or have exactly the same supported behaviours in hardware. This module should be sufficient for most purposes, but check your synthesis results!
NOTE: We place ports A and B in their own always blocks to express they have no priority between them, matching the underlying Block RAMs.
generate // Returns OLD data if (READ_NEW_DATA == 0) begin always @(posedge clock) begin if(wren_A == 1’b1) begin ram[addr_A] <= write_data_A; end read_data_A <= ram[addr_A]; end always @(posedge clock) begin if(wren_B == 1'b1) begin ram[addr_B] <= write_data_B; end read_data_B <= ram[addr_B]; end end // Returns NEW data // This isn't proper, but the CAD tool expects it for inference. // verilator lint_off BLKSEQ else begin always @(posedge clock) begin if(wren_A == 1'b1) begin ram[addr_A] = write_data_A; end read_data_A = ram[addr_A]; end always @(posedge clock) begin if(wren_B == 1'b1) begin ram[addr_B] = write_data_B; end read_data_B = ram[addr_B]; end end // verilator lint_on BLKSEQ endgenerate If you are not using an init file, the following code will set all memory locations to INIT_VALUE. The CAD tool should generate a memory initialization file from that. This is useful to cleanly implement small collections of registers (e.g.: via RAMSTYLE = "logic" on Quartus), without having to deal with an init file. Your CAD tool may complain about too many for-loop iterations if your memory is very deep. Adjust the tool settings to allow more loop iterations. At a minimum, the initialization file format is one value per line, one for each memory word from 0 to DEPTH-1, in bare hexadecimal (e.g.: 0012 to init a 16-bit memory word with 16'h12). Note that if your WORD_WIDTH isn't a multiple of 4, the CAD tool may complain about the width mismatch. You can base yourself on this Python memory initialization file generator. generate if (USE_INIT_FILE == 0) begin integer i; initial begin for (i = 0; i < DEPTH; i = i + 1) begin ram[i] = INIT_VALUE; end end end else begin initial begin $readmemh(INIT_FILE, ram); end end endgenerate endmodule Back to FPGA Design Elements
Verilog HDL: Single-Port RAM Design Example
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Verilog memory code. Synchronous Random Access Memory (RAM). Testbench memory modeling.
In order to vlaidate the verilog ram memory implementation we will implement a model in verilog test-bench to generate the controls. The way we are going to model it is as follows.
Memory Implementation diagram and details
write data/memory contents, read data and analysis. First we are going to fill in the memory with write only commands. The data we are going to write will be random. After filling in the memory, we will enable reads. During reads we will request random addresses between 0 and 63. We will dump both read and write data in text files. Links to test- bench
Single Port RAM Synchronous Read
1 //—————————————————– 2 // Design Name : ram_sp_sr_sw 3 // File Name : ram_sp_sr_sw.v 4 // Function : Synchronous read write RAM 5 // Coder : Deepak Kumar Tala 6 //—————————————————– 7 module ram_sp_sr_sw ( 8 clk , // Clock Input 9 address , // Address Input 10 data , // Data bi-directional 11 cs , // Chip Select 12 we , // Write Enable/Read Enable 13 oe // Output Enable 14 ); 15 16 parameter DATA_WIDTH = 8 ; 17 parameter ADDR_WIDTH = 8 ; 18 parameter RAM_DEPTH = 1 << ADDR_WIDTH; 19 20 //--------------Input Ports----------------------- 21 input clk ; 22 input [ADDR_WIDTH-1:0] address ; 23 input cs ; 24 input we ; 25 input oe ; 26 27 //--------------Inout Ports----------------------- 28 inout [DATA_WIDTH-1:0] data ; 29 30 //--------------Internal variables---------------- 31 reg [DATA_WIDTH-1:0] data_out ; 32 reg [DATA_WIDTH-1:0] mem [0:RAM_DEPTH-1]; 33 reg oe_r; 34 35 //--------------Code Starts Here------------------ 36 37 // Tri-State Buffer control 38 // output : When we = 0, oe = 1, cs = 1 39 assign data = (cs && oe && ! we) ? data_out : 8'bz; 40 41 // Memory Write Block 42 // Write Operation : When we = 1, cs = 1 43 always @ ( posedge clk) 44 begin : MEM_WRITE 45 if ( cs && we ) begin 46 mem[address] = data; 47 end 48 end 49 50 // Memory Read Block 51 // Read Operation : When we = 0, oe = 1, cs = 1 52 always @ ( posedge clk) 53 begin : MEM_READ 54 if (cs && ! we && oe) begin 55 data_out = mem[address]; 56 oe_r = 1; 57 end else begin 58 oe_r = 0; 59 end 60 end 61 62 endmodule // End of Module ram_sp_sr_sw You could download file ram_sp_sr_sw.v here
키워드에 대한 정보 ram verilog code
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